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Journal of Mathematics in Industry

Table 2 List of the 9 test circuits that were taken from concrete circuits

From: A holistic fast and parallel approach for accurate transient simulations of analog circuits

Circuit/solver/# CPU

Elapsed time (s)

# time steps

# Newton iter.

Speedup

cir1/KLU /1

55.05

400

1781

 

cir1/BBD1/1

52.33

422

1861

1.05

cir1/BBD2/1

45.45

418

1895

1.21

cir1/BBD2/2

29.44

423

1929

1.87

cir1/BBD2/4

18.59

419

2026

2.86

cir1/BBD2/8

16.43

412

2013

3.35

cir2/KLU /1

42.72

657

2450

 

cir2/BBD1/1

43.82

657

2438

0.97

cir2/BBD2/1

42.43

686

2545

1.01

cir2/BBD2/2

27.53

655

2453

1.55

cir2/BBD2/4

19.16

707

2574

2.22

cir2/BBD2/8

14.30

659

2467

2.98

cir3/KLU /1

165.95

1920

7803

 

cir3/BBD1/1

139.00

1844

7452

1.19

cir3/BBD2/1

118.44

1870

7673

1.40

cir3/BBD2/2

83.88

1872

7646

1.97

cir3/BBD2/4

62.10

1877

7756

2.67

cir3/BBD2/8

55.92

1845

7655

2.96

cir4/KLU /1

125.01

3206

10,257

 

cir4/BBD1/1

153.48

3213

10,488

0.81

cir4/BBD2/1

151.89

3218

10,488

0.82

cir4/BBD2/2

103.58

3213

10,488

1.21

cir4/BBD2/4

87.31

3213

10,488

1.43

cir4/BBD2/8

71.39

3213

10,488

1.75

cir5/KLU /1

1616.62

892

2987

 

cir5/BBD1/1

510.28

897

3032

3.16

cir5/BBD2/1

508.44

897

3032

3.18

cir5/BBD2/2

354.05

897

3030

4.56

cir5/BBD2/4

268.39

897

3031

6.02

cir5/BBD2/8

256.78

897

3034

6.30

cir6/KLU /1

2482.57

153

893

 

cir6/BBD1/1

225.35

154

880

11.01

cir6/BBD2/1

212.00

147

866

11.71

cir6/BBD2/2

123.13

147

869

20.16

cir6/BBD2/4

81.50

147

875

30.46

cir6/BBD2/8

66.96

147

880

37.10

cir7/KLU /1

2456.89

176

1132

 

cir7/BBD1/1

497.99

176

1132

4.93

cir7/BBD2/1

475.30

180

1164

5.16

cir7/BBD2/2

286.65

180

1164

8.57

cir7/BBD2/4

172.19

180

1164

14.29

cir7/BBD2/8

132.23

180

1164

18.58

cir8/KLU /1

8490.84

484

2964

 

cir8/BBD1/1

2593.06

454

2829

3.27

cir8/BBD2/1

2462.75

463

2879

3.44

cir8/BBD2/2

1846.18

462

2877

4.60

cir8/BBD2/4

1470.81

464

2872

5.77

cir8/BBD2/8

1312.55

458

2854

6.47

cir9/KLU /1

23,238.25

68

193

 

cir9/BBD1/1

1296.32

68

193

17.92

cir9/BBD2/1

1254.30

68

209

18.52

cir9/BBD2/2

1083.28

68

209

21.45

cir9/BBD2/4

870.81

68

209

26.68

cir9/BBD2/8

712.55

68

209

32.61

  1. The base line for comparison is a simulation with the KLU solver [23, 38]. The sequential run with the BBD1 solver is the presented approach but without partition bypassing. The sequential and parallel runs with BBD2 solver represent the full approach with partition bypassing. For each sequential and multi-threaded simulation we enlist the elapsed simulation time on an Intel Xeon 2.9 GHz processor with 12 cores, without considering any setup time of the solver or simulator. Starting from the third column, we enlist the number of time steps, the number of Newton iterations, and the speedup in the elapsed time compared to the KLU solver.
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