Nanoelectronic COupled problems solutions  nanoCOPS: modelling, multirate, model order reduction, uncertainty quantification, fast fault simulation
 E Jan W ter Maten^{1}Email authorView ORCID ID profile,
 Piotr A Putek^{1, 2},
 Michael Günther^{1},
 Roland Pulch^{2},
 Caren Tischendorf^{3},
 Christian Strohm^{3},
 Wim Schoenmaker^{4},
 Peter Meuris^{4},
 Bart De Smedt^{4},
 Peter Benner^{5},
 Lihong Feng^{5},
 Nicodemus Banagaaya^{5},
 Yao Yue^{5},
 Rick Janssen^{6},
 Jos J Dohmen^{6},
 Bratislav Tasić^{6},
 Frederik Deleu^{7},
 Renaud Gillon^{7},
 Aarnout Wieers^{7},
 HansGeorg Brachtendorf^{8},
 Kai Bittner^{8},
 Tomáš Kratochvíl^{9},
 Jiří Petřzela^{9},
 Roman Sotner^{9},
 Tomáš Götthans^{9},
 Jiří Dřínovský^{9},
 Sebastian Schöps^{10},
 David J Duque Guerra^{10},
 Thorben Casper^{10},
 Herbert De Gersem^{10},
 Ulrich Römer^{10},
 Pascal Reynier^{11},
 Patrice Barroul^{11},
 Denis Masliah^{11} and
 Benoît Rousseau^{11}
https://doi.org/10.1186/s1336201600255
© ter Maten et al. 2016
Received: 10 February 2016
Accepted: 20 June 2016
Published: 30 June 2016
Abstract
The FP7 project nanoCOPS derives new methods for simulation during development of designs of integrated products. It covers advanced simulation techniques for electromagnetics with feedback couplings to electronic circuits, heat and stress. It is inspired by interest from semiconductor industry and by a simulation tool vendor in electronic design automation. The project is ongoing and the paper presents the outcomes achieved after the first half of the project duration.
Keywords
1 Introduction

PowerMOS devices, with applications in energy harvesting, that involve couplings between electromagnetics (EM), heat and stress, and

RFcircuitry in wireless communication, which involves EMcircuitheat coupling and multirate behaviour, together with analoguedigital signals.

create efficient and robust simulation techniques for strongly coupled systems, that exploit the different dynamics of subsystems within multiphysics problems and that allow designers to predict reliability and ageing;

include a variability capability such that robust design and optimization, worst case analysis, and yield estimation with tiny failure probabilities are possible (including large deviations like 6sigma);

reduce the complexity of the subsystems while ensuring that the operational and coupling parameters can still be varied and that the reduced models offer higher abstraction models that are efficient to simulate.
First outcomes have been reported in [1, 2]. The project is ongoing and the paper presents the outcomes achieved after the first half of the project duration. Recently, at the DATE2016 conference in Dresden, Germany, we gave dedicated presentations to designers and to engineers with backgrounds in mathematics and in electronics [3–7]. On the project website http://www.fp7nanocops.eu/ special videos have been made available. Here also more publications can be found. The current paper addresses mathematicians and points out how mathematics as essential ingredient for innovation is transfered for successful use in industry.
With the new techniques it is possible to efficiently analyze the effects due to variability. Our methods are designed to solve reliability questions resulting from manufacturability. They facilitate robust design as well as enable worst case analysis. They can also be used to study effects due to ageing. Ageing causes variations in parameters over a longterm period, which cannot be predicted exactly and thus are typically uncertain. The challenges for an Integrated Circuit (IC) are that each device has its own electrical and thermal conditions, which are changing over time (due to ageing, for example). Here, each device has its own required lifetime.
Novel Model Order Reduction techniques, developed here for the fast repeated simulation of the coupled problems under consideration, are applicable to both coupled systems and parameterized subsystems. As such they are an essential ingredient for the Uncertainty Quantification.

advanced cosimulation/multirate/monolithic techniques, combined with envelope/wavelet approaches;

new generalized techniques in Uncertainty Quantification (UQ) for coupled problems, tuned to the statistical demands from manufacturability;

enhanced, parametric Model Order Reduction techniques for coupled problems and for UQ.
Partners in nanoCOPS
Abbr.  Partner 

BUW  Bergische Universität Wuppertal, Germany (coordinator) 
HUB  Humboldt Unversität zu Berlin, Germany 
TUD  Technische Universität Darmstadt, Germany 
UGW  ErnstMoritzArndtUniversität Greifswald, Germany 
FHO  FH OÖ Forschungs und Entwicklungs GmbH, Hagenberg im Mühlkreis, Upper Austria, Austria 
KUL  Katholieke Universiteit Leuven, Belgium 
BUT  Vysoké uc̆ení technické v Brnĕ, Brno University of Technology, Czech Republic 
MPG  Max Planck Institute for Dynamics of Complex Technical Systems, Magdeburg, Germany 
NXP  NXP Semiconductors Netherland B.V., Eindhoven, The Netherlands 
ONN  ON Semiconductor Belgium, Oudenaarde, Belgium 
MAG  MAGWEL NV, Leuven, Belgium 
ACC  ACCO Semiconductor, Louveciennes, France 
2 Progress and results
In this section we give an impression of outcomes achieved in the first half of the project duration. We refer with the abbreviations in Table 1 to the various project partners.
2.1 Simulation environment
Electronic devices consist of a large number of components. Many parts are accurately described by a circuit model, whereas semiconductor parts and configurations suffering from electromagnetic interference necessitate the use of field models. The overall behaviour of the device needs to be simulated by a fieldcircuit coupled method. Improvements on such coupled techniques indirectly lead to more reliable and better integrated devices. In order to be able to incorporate the mutual electromagnetic influence of neighboring elements (e.g., cross talking), one needs refined models based on a sufficiently exact discretization of the full Maxwell equations. An interface model for such refined models was derived that can be used for lumped circuit net lists.
2.2 Bondwire modelling and simulation
ONN and BUT made measurements of DC and dynamical fusing of bondwires [16]. ONN fabricated test chips (SOIC package so far), where the individual bondwires with different lengths, diameters and materials have been encapsulated. BUT prepared a complete methodology and experimental setup to do such investigations.
The setup (hardware tester and MATLAB GUI) allows measurements of all six bondwires in one IC package. The tester consists of the 6 independent channels, the 6 driving stages, the 6 Kelvin probe sensing stages, the demultiplexing core for the driving stages (specification of address of the bondwire) and the multiplexing core for the Kelvin probe sensing stages.
2.3 Electrothermal coupled simulation
2.4 Multirate simulations
In coupled problems one often encounters multiscale differences (in space) and large variations in dynamics in timedomain: multirate effects [17]. In this book especially partitions in space with different dynamics lead to couplings between subsets of DAEs. A careful formulation of the coupling is key in being able to guarantee convergent dynamical iterations in a cosimulation. In [9] the partition between physical quantities (electromagnetics, heat) was exploited to study this convergence.
Performance summary multirate simulation
Single grid  Multiple grids  

Number of equations  130,000  85,000 
Nonzeros in Jacobian  5 × 10^{6}  2.5 × 10^{6} 
Assembly of linear system  4 s  2 s 
Linear solve  8 s  4 s 
Envelope analysis  5 h  37 min 
2.5 Parametric model order reduction
2.6 Uncertainty quantification
We finally remark that our implementations are also able to identify dominant parameter contributions to the variance when varying parameters [28].
As a separate action, TUD developed a GUI (Graphical User Interface) for Uncertainty Quantification to easily compare our UQ methods with Monte Carlo simulations and Worst Case Corner Analysis [29]. The last approach is very popular in the semiconductor industry because it is much faster than Monte Carlo. Our UQ implementation exploits sparse grid techniques and can easily deal with up to 20 independent parameters.
2.7 Fast fault simulation
NXP, BUW and TU Eindhoven developed a special algorithm for fast fault simulation in NXP’s inhouse circuit simulator Pstar. NXP’s simulator is the best in the world for this functionality [7, 30]. Imperfections in manufacturing processes may cause unwanted connections (faults) that are added to the nominal, ‘golden’, design of an electronic circuit. When considering faults from the point of view of parameter variations this is well in the range of large deviations. In [30] the faulty elements are represented by adding linear conductivities to the circuit. The approach also works for analyzing the effect of additional linear capacitors. However, the main interest is in adding linear conductivities: thus \(p{u}{v}^{T} {x}(t,p)\), where \(p=1/R\), with resistance R, and given vectors u, v, to the system of circuit equations of which the solution becomes \({x}(t,p)\). By fault simulation we simulate all situations: a huge number of new connections of pairs of vectors \(({u},{v})\) and each with many different values of p, up to the regime of large deviations, for the newly added element and comparing the result \({x}(t,p)\) at specific time points with the ‘golden’ solution \(\tilde{x}(t)={x}(t, 0)\) of the faultfree circuit, corresponding with \(p=0\). If the deviation between \({x}(t,p)\) and \(\tilde{x}(t)\) exceeds some threshold, the fault triple \(({u},{v}, p)\), is marked as detectable and is taken out of the list. We also consider ‘opens’ (broken connections). A strategy is developed to efficiently simulate the faulty solutions until their moment of detection. The hierarchical structure was enhanced, such that the hierarchical solver could deal with all new elements: note that some new connections may violate the original hierarchical structure of the golden circuit. A clever software solution was developed and is reported in [30]. By this, also the faulty problems could benefit from an enhanced form of hierarchical bypassing. Because each candidate fault is a lowrank modification of the designed circuit an hierarchical variant of the ShermanMorrison formula was exploited. Fast fault simulation is achieved in which the golden solution and all faulty solutions are calculated over the same time step.
The results are stored in a database. This database is of help to first externally diagnose a faulty IC and to identify the candidate circuit submodels where the fault may have happened. After that the IC can be studied further internally. This can help to improve next productions. Moreover, the collection of simulations can also be helpful as a priori check before layouting. NXP can identify locations on a chip that are probably affected by tiny manufacturing accuracies, which case faulty behaviour at predefined time points for measurements.
Note that essentially one is looking to the weak spots in the circuit. In our approach the manufacturing process is the immediate cause of the problem. However it can also show up later, due to effects of ageing of the design, or by stress effects due to heating. It is also related to other network problems, e.g., in analyzing traffic behaviour in a city when suddenly a road is blocked, or when a new connection pops up. Our approach can be extended to energy distribution networks, sewage systems, and even to networks that are not constant of size in time.
This algorithm also offers interesting ingredients to combine with Uncertainty Quantification.
2.8 Test examples, measurements
The industrial partners NXP, ONN, and ACC did provide various test examples. The test cases cover realisticsize power MOS devices at constant temperature and in ET coupling mode; a driver chip with multiple heatsources; a smart power driver test chip with thermal sensor; an 8shaped inductor with surrounding circuitry; a fast and reliable model for bondwire heating; RF and electrothermal simulations; reliable RFIC isolation under uncertainty (for floor planning and grounding strategies; this involves onchip coupling effects, chippackage interaction, substrate coupling and the socalled cohabitation factor); multirate circuit examples; silicon test chips for stepbystep testing and validation; transmission line and baluns. All these are found in our industrial problem classes described in the introduction. ACC has prepared several designs, made simulations and realized test boards. They served for step by step study, for comparison to measurements and for validation of the enhanced MAGWEL software, in close cooperation with BUT, NXP and ONN.
As simple example, we mention here test chips that include passive structures (inductances, capacitances, baluns, resonators). These structures, that are easily measurable, are used to validate further EM extraction and model reduction. Simulated results are compared to measurements, EM solver extraction and then with extraction plus netlist reduction in terms of accuracy, memory usage and time simulation.
3 Conclusion

The coupling interface with the MAGWEL software has been improved, tested and is operational.

Successful largescale EMheat simulation was achieved.

Gridadaptive multirate circuit simulation was established.

Model Order Reduction was successfully applied to coupled EMheat problems.

Accurate bond wire modelling for fast usage at industry was demonstrated and was validated by measurements.

Uncertainty Quantification was applied to variations of material parameters and geometry and was used in robust topology optimization. Apart from the topics, this at best demonstrates the robustness of the integrated software  to achieve optimization one addresses all parts of the codes.

Innovative methods for improving yield as well as to identify faults were derived.

Advanced measurements environments have been set up both at academia and at industry.

Outcomes have been presented at conferences. Joint papers have been published in various journals.

Interaction between academia and industrial partners addressed a broad range: test examples, new algorithms, implementations, practical use of new methods, ways to improve measurements.
Declarations
Acknowledgements
This FP7 Collaborative Project nanoCOPS is supported by the European Union in the FP7ICT201311 Programme under Grant Agreement Number 619166 (Project nanoCOPS  nanoelectronic COupled Problems Solutions). For further details see http://www.fp7nanocops.eu/.
Open Access This article is distributed under the terms of the Creative Commons Attribution 4.0 International License (http://creativecommons.org/licenses/by/4.0/), which permits unrestricted use, distribution, and reproduction in any medium, provided you give appropriate credit to the original author(s) and the source, provide a link to the Creative Commons license, and indicate if changes were made.
Authors’ Affiliations
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